1. Field of the Invention
The present invention relates to a known good die array (hereinafter referred to as a "KGD" array) and manufacturing method thereof, and more particularly to a KGD array and manufacturing method thereof, wherein a plurality of integrated circuit chips (hereinafter referred to as "IC chips"), which are separated from a wafer are simultaneously subjected to an alternating current (AC) or burn-in test, thereby enabling mass production of KGD arrays without defects.
2. Description of the Prior Art
It is known that IC chips are essentially subjected to an AC test or burn-in test during the manufacture of semiconductor devices for the purpose of finding defective IC chips. However, bare IC chips cannot be connected to a test pattern generating circuit, and thus, the AC test or burn-in test cannot be performed. Therefore, as shown in FIG. 1, the general AC test and burn-in test are carried out when packaged by molding the IC chip by a molding process using an epoxy molding compound ("EMC").
Referring to FIG. 1, external leads 12 connected to chip pads (not shown) project along sidewalls of a package 10. A test socket 15 for mounting the package 10 has a plurality of receptacles 14 to receive the external leads 12. Rigid leads 16 externally project from the lower portion of the receptacles 14.
The package 10 having the projecting external leads 12 is mounted in the receptacles 14 of the test socket 15. The test socket 15 is fixed to a burn-in-board which is not shown. Thus, the AC test and burn-in test are performed while the package 10 is mounted in the test socket 15.
During the AC test and the burn-in test, the IC chip is supplied with test signals at elevated temperatures or at voltage levels higher than that used for normal operation. Then, a check is conducted to determine if defects appear in any IC chip when being supplied with the test signal. For example, in a DRAM, defective storage circuits, defective storage cells and defective connection lines could be checked.
Defects such as a breakdown of an insulating layer due to a gate oxide defect, which sometimes appear in IC chips are likely to cause a failure of the chip when used under normal conditions. Therefore, such a defect in an IC chip can be detected by performing the burn-in test, and can be treated as an inferior product. As described above, the defective IC chip is rejected before being sold in the market, thereby guaranteeing reliability of the product stream.
However, since a packaged semiconductor chip is subjected to a burn-in test, once the chip is found to be defective, it cannot be used.
For this reason, instead of utilizing a single chip package, a multi-chip technique has been recently proposed which uses a flip chip for thermally mounting a plurality of bare chips on a ceramic board. The multichip technique includes various integration methods enabling large-scale integration while achieving high speed, high capacity and small size. One representative method among these is an integration method using a multichip module.
The multichip module attains very large scale integration in such a manner that a plurality of IC chips are commonly-connected to a multi-layered ceramic or plastic board having densely-arranged interconnections on the lower portion thereof. Currently, the multichip module is successfully used in super computers, etc., by companies such as IBM, DEC ad Hitachi.
Despite this advantage, the multichip module is technically and economically limited because of the following reasons. As compared with the single chip package technique, the multichip module having a plurality of IC chips has an increased integration scale but the production yield is significantly decreased thereby greatly increasing the manufacturing cost. Because of this, the multichip module has had difficulty in securing a sufficient market. The most difficult problem of the multichip module is to acquire sufficient KGD (i.e., IC chips which are not packaged but which have proved to be reliable after completing testing at the same level as the conventional package technique), which directly relates to the production yield.
The present invention is directed to acquiring sufficient KGD at low cost. Hereinafter, bare IC chips which prove to have no defects after being subjected to all tests will be referred as KGD. The bare chip denotes a common IC chip which is not packaged after being separated from the wafer as a single chip, such as, a flip chip, wire chip, etc. The more detailed concept of the KGD is described in a technical disclosure titled "Potential Project Report", published in October 1992 by Microelectronic and Computer Technology Corporation of Austin, Tex.
Even though the importance of KGD for use in the multichip module has been heightened, the mass production of low-priced KGD is very difficult. In more detail, a single bare chip separated from the wafer has no external leads for use in a test socket for testing the chips. Consequently, the AC test and burn-in test cannot be carried out before the IC chip is installed on a circuit board in the bare chip condition.
As a technique for solving this problem, a flip chip test socket adapter has been proposed which allows for the AC test and burn-in test in the bare chip state. The flip chip socket provides a solder bump to each electrode pad of the chip. This technique is disclosed in U.S. Pat. No. 5,006,792, and illustrated in FIGS. 2 and 3.
FIG. 2 is a perspective view showing a conventional flip chip having solder bumps 24. FIG. 3 is a sectional view showing the flip chip of FIG. 2 mounted to the test socket adapter. Referring to FIG. 2, an IC chip 22 includes a bonding pad having a plurality of solder bumps 24 thereon. The IC chip 22 is inserted into its own test socket adapter which will be described with reference to FIG. 3, and then tested.
Referring to FIG. 3, the test socket adapter 20 includes a substrate 28 having cantilever beams 26 correspondingly connected to the solder bumps 24 of the inserted IC chip 22. A reference numeral 23 denotes a lead connected to the cantilever beam 26. A lead 23 projects to the outside of the case 20, and a guide bar 25 stably supports the IC chip 22 when the IC chip 22 is inserted into the adaptor.
Tests of the IC chip using the test socket adapter according to the above description allows for testing under the bare chip state prior to being packaged.
In the conventional technique, the individual IC chip is separated from the wafer, and the chip test and burn-in test must be performed in the bare chip state while the solder bump 24 which is a metal projection is formed for each electrode pad of the IC chip 22. But an expensive apparatus requiring high precision is necessary during the formation of the bump on the electrode pad of the signal IC chip due to a fine pitch between the electrode pads in chips.
Another problem is that the chip should be individually handled during the test which makes chip handling difficult.
The problems in manufacturing KGD according to conventional techniques may be summarized as follows:
(1) Since the ordinary IC chip cannot be subjected to the AC test and burn-in test, resulting solder bumps must be formed and the chip placed in its own test socket so that the resulting products are provided in small quantity. PA1 (2) Each IC chip is individually handled which makes chip handling difficult. PA1 (3) KGD is considerably more expensive when compared with the packaged IC chip. PA1 (4) It is difficult to form a test jig. PA1 (5) There is no standardized IC chip size having standardized die pad locations.